This invention relates to memory devices, and, more particularly, to a circuit and method for accelerating the propagation of signals in memory devices.
The speed at which digital signals can propagate through integrated circuits, such as memory devices, is often a primary factor limiting the speed at which integrated circuits can operate. As the speed requirements of memory devices and other integrated circuits continues to increase, increasing the speed at which signals can propagate through conductive lines in integrated circuits has become increasingly important. The speed at which digital signals can propagate through signal lines is reduced as the capacitance and/or resistance of the lines increase. In general, both the capacitance and the resistance of a signal line are directly proportional to its length. Since the delay of a signal line is proportional to the product of capacitance and resistance, the delay of the signal line is proportional to the square of its length.
Another requirement of integrated circuits is increased density of semiconductor features. Increasing the density of semiconductor features inevitably results in a reduction in both the thickness of signal lines and the spacing between signal lines. However, reducing the thickness of signal lines increases their resistance, and reducing the spacing between signal lines increases their capacitance. As mentioned above, both increasing capacitance and increasing resistance reduce the propagation speed of signals through the signal lines. This problem is often exacerbated by the need to maintain the cross-sectional area of signal lines constant as their thickness decreases, thus requiring that the lines be made taller. Yet taller lines present a greater surface area to adjacent lines, thus further increasing the line capacitance. Thus, greater feature densities and faster operating speeds are, to some extent, mutually exclusive.
One area where the propagation of digital signals is particularly problematic is the coupling of data, address and control signals in memory arrays. Memory arrays must be very dense to provide acceptable memory capacities, thus making signal lines very thin and close together. The high density of memory arrays thus limits the speed at which data, address and control signals can propagate through memory arrays. Further, propagation delays are also increased by signals in adjacent lines transitioning in opposite directions. When a signal in one line transitions from low to high and a signal in an adjacent line transitions from high to low, for example, capacitive coupling of the transitions between the lines slows the propagation of both signals through their respective lines. Finally, the length of signal lines in memory arrays are relatively long, and a memory operation cannot be completed until the data, address and control signals have propagated to the farthest distance in the array.
It is well recognized that the propagation speed of one edge of a digital signal can be accelerated by coupling the signal through an inverter having xe2x80x9cskewedxe2x80x9d switching characteristics. A skewed inverter is designed so that it switches at a voltage level that is closer to one logic level than the other logic level. With reference to FIG. 1, an inverter 10 is formed by a PMOS transistor 12 and an NMOS transistor 14 coupled in series between a supply voltage VCC, which is typically about 3 volts, and ground potential. When a input signal IN applied to the gates of the transistors 12, 14 is low, i.e., ground potential, the PMOS transistor 12 is turned ON and the NMOS transistor 14 is turned OFF, thereby producing a high, i.e., VCC level, output signal OUT. When the input signal is high, i.e., VCC level, the PMOS transistor 12 is turned OFF and the NMOS transistor 14 is turned ON, thereby producing a low, i.e., ground potential, output.
In a skewed inverter, one of the transistors 12, 14 is fabricated differently from the other of the transistors 12, 14. For example, the channel of one transistor 12, 14 may be fabricated with a channel that is wider or longer than the channel of the other one of the transistors 12, 14, the doping concentrations of the transistors 12, 14 may be different, or the transition voltage VT of the transistors 12, 14 may be different. In the case of the inverter 10 of FIG. 1, the NMOS transistor 14 has a channel that is wider than the channel of the PMOS transistor 14. As a result, the NMOS transistor 14 has a smaller resistance than the PMOS transistor 12 with the same gate-to-source voltage VGS. The switching characteristics of the inverter 10 are shown in FIG. 2, using a voltage level of VCC equal to 3 volts, although other levels of VCC may be used. When the input signal IN is at 1.5 volts as it transitions from ground to 3 volts, the NMOS transistor 14 has a lower resistance than the PMOS transistor 12 because of its increased channel width. Consequently, the output signal OUT has already transitioned to ground potential. The output signal OUT has thus switched from high to low before the input signal IN has switched from low to high. The inverter 10 accelerates the input signal IN because the falling edge of the output signal OUT occurs before the rising edge of the input signal IN. If this phenomena was true for both the rising edge and the falling edge of the IN signal, a digital signal could be accelerated simply by connecting a number of skewed inverters in series. Unfortunately, such is not the case. With further reference to FIG. 2, when the input signal IN is at 1.5 volts as it transitions from 3 volts to ground, the NMOS transistor 14 continues to have a lower resistance than the PMOS transistor 12. As a result, the output voltage OUT remains at ground potential. The output signal OUT thus switches from low to high well after the input signal IN has switched from high to low. An inverter could be designed to accelerate the falling edge of the input signal IN by making the channel width of the PMOS transistor 12 greater than the channel width of the NMOS transistor 14. However, doing so would then delay the rising edge of the input signal IN. Thus, skewed inverters inherently accelerate one edge of a digital signal only at the expense of delaying the other edge of the digital signal. It is therefore apparent that skewed inverters alone cannot be used to accelerate digital signals in integrated circuits, such as memory devices.
A high speed signal path includes a first plurality of inverters skewed toward a first polarity of signal transition alternating with a second plurality of inverters skewed toward a second polarity of signal transition. As a result, each of the inverters in the first set accelerates a transition from a first logic level to a second logic level, and each of the inverters in the second set accelerates a transition from the second logic level to the first logic level. A pass gate preferably couples an input terminal to the first inverter in the series responsive to a control signal having a first value. A preset circuit presets the inverters to a logic level so that any subsequent transition of the inverters resulting from coupling a digital signal through the inverters will be accelerated. A pair of the high speed signal paths may be used to couple a digital signal and a clock signal to respective output terminals. By designing the high speed signal path for the digital signal with greater skew than the high speed signal path for the clock signal, the digital signal will be present at its output terminal for a period that encompasses the period that the clock signal is present at its output terminal. As a result, the clock signal can be used to designate a data valid period for the digital signal. The high speed signal path may be used in memory devices or other integrated circuits, and a memory device using one or more of the high speed signal paths may be used in a computer system.